Integrated circuits typically include a plurality of layers comprising different materials. These layers are formed or deposited using a variety of different processes. These deposited layers are patterned to form final designs and the patterning of the deposited layer includes etching processes.
Since the formation of integrated circuits involves many, sometimes hundreds of process steps, controlling the failure rate in each of the process steps becomes vitally important. When a failure occurs, the failed components need to be identified. Further research is then performed to find the reasons of the failure and to determine how process steps can be adjusted to avoid the failure.
The failures, however, are sometimes subtle, and may only occur to some of the integrated circuits (products), but not to other circuits. The process steps thus need to be customized to solve these product-specific problems. For example, in some of the input/output (IO) chips, it was found that the joint test action group (JTAG) failure rate is particularly high, sometimes as high as about 12 percent to about 18 percent. Solutions to these types of problems are thus needed.